The thyristors is an indispensable device for high power use due to its low on-voltage. In these days, many gate turnoff (GTO) thyristors are used in the high-voltage high-current region. However, some demerits of the GTO thyristor have also become tangible; a large gate current is necessary for turning off the GTO thyristor, i.e. the turnoff gain is small, and a large snubber circuit is necessary for safe turnoff of the GTO thyristor. Since the GTO thyristor does not exhibit current saturation in its current/voltage characteristics, it is necessary to connect a fuse and such passive parts for load short-circuit protection. This is very hazardous for down-sizing of the system and for cost reduction. V. A. K. Temple disclosed a MOS controlled thyristor (MCT), classified into a voltage-driven-type thyristor, in IEEE IEDM Tech. Dig. (1984), p282. Since then, analyses and improvements of the MCT have been conducted in various laboratories, world wide. Since the MCT is of voltage-driven-type, the MCT uses a much simpler gate circuit than that for GTO thyristors and exhibits lower on-voltage than those of the GTO thyristors. However, the MCT also requires a fuse and such passive parts in practical use, since the MCT does not exhibits current saturation in the current/voltage characteristics as the GTO thyristor. M. S. Shekar et al. revealed experimentally in IEEE Electron Device Lett. Vol. 12 (1991), p287 that a dual-channel-type emitter switched thyristor (EST-1) exhibits current saturation up to a high voltage region. The inventors of the present invention disclosed in Proc. IEEE ISPSD, '93, p71 and Proc. IEEE ISPSD, '94, p195 the analytical results of the EST in the forward bias safe operation area (FBSOA) and the reverse bias safe operation area (RBSOA), and opened up for the first time a way for developing a device which still has a safe operation area even when a load short circuit is caused. FIG. 41 shows the device structure of this EST device.
Referring now to FIG. 41, the device includes a p-type emitter layer 1, an n-type buffer layer 2 on p-type emitter layer 1, and an n-type base layer 3 on n-type buffer layer 2. A first p-type base region 4, a p.sup.+ base region 5 which occupies a part of p-type base region 4 and has a deeper diffusion depth than p-type base region 4, and a second p-type base region 6 are in the surface portion of n-type base layer 3. An n-type source region 7 is in the surface portion of the first p-type base region 4, and an n-type emitter region 8 in the surface portion of the second p-type base region 6. A gate electrode 10 is disposed via a gate insulation film 9 on the device from the portion of p-type base regions 4 extending between n-type source region 7 and the extended portion of n-type base layer 3 between the first and second p-type base regions 4 and 6 to the portion of p-type base region 6 extending between n-type emitter region 8 and the extended portion of n-type base layer 3. These constituents are finite in length in Z-direction of the figure. The first and second p-type base regions 4 and 6 are connected with each other at their far ends of the figure. An L-shaped p.sup.+ base region 5 is formed outside the first and second p-type base regions 4 and 6. A cathode 11 contacts commonly with the surfaces of p.sup.+ base region 5 and n-type source region 7. An anode 12 is disposed on the entire back surface of p-type emitter layer 1.
An inversion layer (partial storage layer) is created below gate insulation film 9 and a lateral MOSFET is turned on by applying a positive voltage to gate electrode 10 under the state that cathode 11 is grounded and a positive voltage is applied to anode 12. At first, electrons flow from cathode 11 to n-type base layer 3 via n-type source region 7 and the channel in the surface portion of p-type base regions 4. The electrons work as a base current of a pnp transistor consisting of p-type emitter layer 1; n-type buffer layer 2 and n-type base layer 3; and p-type base region 4, p-type base region 6 and p.sup.+ base region 5, and the pnp transistor operates. Holes are injected from p-type emitter layer 1. A part of the injected holes flows to p-type base region 6 via n-type buffer layer 2 and n-type base layer 3. Then, the holes flow below n-type emitter region 8 in Z-direction to cathode 11 putting the device in the IGBT mode. As the current further increases, the pn junction between n-type emitter region 8 and p-type base region 6 is biased forward and the thyristor portion consisting of p-type emitter layer 1; n-type buffer layer 2 and n-type base layer 3; and p-type base region 6 and n-type emitter region 8 is latched up. In turning off the EST, the potential of gate electrode 10 is lowered below the threshold voltage of the lateral MOSFET to turn off the lateral MOSFET. As a result, the potential of n-type emitter region 8 is disconnected from that of cathode 11, and the thyristor stops operating.
FIGS. 42 and 43 show the improved EST's disclosed by M. S. Shekar et al. in the U.S. Pat. No. 5,317,171 and U.S. Pat. No. 5,319,222. The improved EST of FIG. 43 is different from the EST of FIG. 41 in that the EST of FIG. 43 aims at a lower on-voltage.
FIG. 44 shows a FET controlled thyristor disclosed by Leipold et al. in the U.S. Pat. No. 4,502,070.
Since the EST of FIG. 41 biases forward the pn junction between the second p-type base region 6 and n-type emitter region 8 by utilizing the holes which flow in the second p-type base region 6 in Z-direction as explained above, the degree of forward bias is smaller as nearer to the contact portion of cathode 11 and p-type base region 6. To say in other wards, in the pn junction, the injection amount of electrons from n-type emitter region 8 varies along Z-direction. When the EST is turned off under such an on-state, the junction recovers naturally from the shallowly biased contact portion with cathode 11 and delays recovering in the portion far from the contact portion with cathode 11. This causes current localization in turning-off and lowers the breakdown withstand capability at turning-off.
Though the operation principle of the device of FIG. 42 is not different from that of the EST of FIG. 41, the device of FIG. 42 facilitates quick turning-off, since a cathode 11 extends in Y-direction and contact directly with the surface of the second p-type base region 6. The device of FIG. 42 also facilitates quick turning-on, since the device of FIG. 42 does not utilize the hole current in Z-direction. However, the on-voltage does not lower so much as expected, since uneven minority carrier injection is caused in the horizontal direction Y-direction) even when the pn junction between an n-type emitter region 8 and a p-type base region 6 turns on. If the resistance of p-type base region 6 is increased to solve the foregoing problem, e.g., by lowering the impurity concentration in p-type base region 6, a depletion layer will punch through n-type emitter region 8 when a forward blocking voltage is applied and a sufficiently high breakdown voltage will not be obtained.
In the device of FIG. 43, an n-type emitter region 8 is extended outside a p-type base region 6 to further lower the on-voltage. However, this structure can not provide the device with a sufficient forward blocking voltage.
The device of FIG. 44 solves the above described problem by separating an n-type emitter region 8 and p-type base region 6 completely from a cathode 11. However, a depletion layer does not expand from p-type base region 6 when a forward bias voltage is applied, since the electrical potentials of n-type emitter region 8 and p-type base region 6 are floating. Therefore, the breakdown voltage characteristics of the device of FIG. 44 are inferior to those of the improved EST's.
In view of the foregoing, it is an object of the present invention to provide an insulated gate thyristor having a structure which facilitates uniform recovery of the pn junction at turning-off. It is another object of the invention to provide an insulated gate thyristor which exhibits large turnoff withstand capability, small on-voltage and excellent breakdown voltage characteristics.